This invention relates generally to the field of semiconductor devices and, more specifically, to a method for manufacturing a bipolar junction transistor.
Semiconductor devices are used for many applications, and one component used extensively in semiconductor devices is a transistor. There are many different types of transistors, including a bipolar junction transistors. Bipolar junction transistors can be used to make other types of transistors or devices, such as super self-aligned transistors, which are the most efficient bipolar structures to maximize performance.
Many processes are used to manufacture super self-aligned transistors. One such process is etching. For example, etching is used in the manufacturing of super self-aligned transistors to etch polysilicon on single crystal silicon. The etching of polysilicon on single crystal silicon is extremely difficult and ends up in a very small operating process window. A problem with the etching of polysilicon on single crystal silicon is that over-etching or under-etching may occur. Over-etching or under-etching hurts reliability of super self-aligned transistors and reduces yield.
Therefore, semiconductor manufacturers desire a method of etching polysilicon on single crystal silicon that substantially reduces or eliminates over-etching or under-etching.
The challenges in the field of semiconductor devices continue to increase with demands for more and better techniques having greater flexibility and adaptability. Therefore, a need has arisen for a new method for manufacturing a bipolar junction transistor.
In accordance with the present invention, a method for manufacturing a bipolar junction transistor is provided that addresses disadvantages and problems associated with previously developed methods.
According to one embodiment of the invention, a method for manufacturing bipolar junction transistors includes disposing a first oxide layer between a semiconductor substrate and a base polysilicon layer, forming a dielectric layer outwardly from the base polysilicon layer, and forming an emitter region by removing a portion of the dielectric layer and a portion of the base polysilicon layer. The method further includes removing a portion of the first oxide layer to form undercut regions adjacent the emitter region and to enlarge the emitter region, and forming an oxide pad outwardly from the semiconductor substrate in the emitter region.
Embodiments of the invention provide numerous technical advantages. For example, a technical advantage of one embodiment of the present invention is that a process margin for over-etching is provided by utilizing selective oxidation to form an etch stop where polysilicon is to be etched on single crystal silicon. Another technical advantage of one embodiment of the present invention is that the etch stop substantially reduces or eliminates under-etching, as well as over-etching, thereby increasing the reliability and yield of semiconductor devices having bipolar junction transistors.
Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.